The present invention relates to a nonvolatile semiconductor memory device having a redundant function of relieving a defective portion inside a memory cell array by substituting a reserved or relief portion (redundancy) for the defective portion, and in particular, to a circuit incorporated in such a nonvolatile semiconductor memory device for storing and latching the address data of the defective portion.
In connection with nonvolatile semiconductor memory devices, there is a known method for replacing defective bit lines, defective word lines and defective memory cells with reserved normal ones (redundancy) to increase the yield. In the nonvolatile semiconductor memory device utilizing such a method, the addresses of the defective bit lines, the defective word lines and the defective memory cells, i.e., the defective address data are required to be stored.
(First Related Background Art)
To store the data representing the defective address, use of electrically rewritable nonvolatile semiconductor memory cells is known from Japanese Patent Application Laid-Open No. 5-276018. An example of such a method is described below with reference to FIG. 25 showing a circuit for storing and latching the defective address data. For example, the case in which an address "101" is stored in this circuit is described below. The circuit shown in FIG. 25 is adapted to a flash memory, represented by ETOX.TM., to which writing is executed by using a channel hot electron. In the conventional flash memory of this type, memory cells M0, M1, and M2 in an initial state have a threshold (gate threshold voltage) of about 0.5 volts to 2.5 volts.
The writing or programming is executed by using channel hot electrons as follows. Initially, an H(high)-level equivalent to a value of "1" is supplied to a data line DL shown in FIG. 25. Then, an L(low)-level is latched in a write data latch circuit DLC. On the other hand, the potential of a word line WL for the memory cells M0, M1, and M2 rises to a Vpp (for example, 10 volts), and the potential of a bit line selection signal bitsel0 has also the potential Vpp. At this time, 0 volts is output from a level shifter HV, with a bit line BL0 having a floating state and the threshold of the memory cell M0 kept at the low voltage (2.5 volts or less). Then in writing data "0", an L-level is supplied to the data line DL, an H-level is latched in the write data latch circuit DLC, and the potential of the word line WL of the memory cells rises to the Vpp level. The potential of the bit line selection signal bitsell also becomes the Vpp level. The output of the level shifter HV, in which the H-level is latched, assumes the potential Vpp. Thus, a voltage hhprg (for example, 6 volts) is output to a bit line BL1. As a result, the threshold of the memory cell M1 rises to a voltage of 5 volts or more owing to the channel hot electrons, as shown in FIG. 20. The memory cell M2 is kept in a low-threshold state, similar to the memory cell M0.
The operation of the defective address latch circuit ALC (ALC0, ALC1, ALC2) upon turn-on of the power supply of the memory device will be described below with reference to FIGS. 21A, 21B, 22A, and 22B. FIGS. 21A and 21B each show a circuitry of a basic cell for storing one bit of the defective address data. First, when the data "0" is stored in the memory cell M1, as shown in FIG. 21B, as a supply voltage Vcc rises, the potential of a node A increases owing to coupling, following the supply voltage Vcc, as indicated by a power supply turn-on waveform of FIG. 22B. Because the threshold, Vth, of the memory cell M1 is 5 volts or more in this case, the memory cell M1 is off and electric current does not flow therethrough, and an output radd1 latches and supplies a "0".
Referring to FIG. 21A, the memory cells M0 and M2 store the data "1". Thus, as indicated by a power supply turn-on waveform of FIG. 22A, once the word line has a voltage of 2.5 volts or more, electric current starts to flow through the memory cells M0 and M2, and the node A, which initially followed the supply voltage Vcc, drops to the level L. This is because electric current flows through the memory cells M0 and M2. As a result, outputs radd0 and radd2 have a "1"-latched state, respectively.
(Second Related Background Art)
In the first related background art, one bit of address information is stored by one memory cell. Another method for storing address information is known from Japanese Patent Application Laid-Open No. 8-22699, in which two memory cells are used to store one bit of address information. An example of such a method is described below with reference to FIG. 26 on the case in which an address "101" is stored in the circuit of FIG. 26. The circuit shown in FIG. 26 is applied to a flash memory (represented by ETOX.TM.) to which programming is executed using a channel hot electron. In the known flash memory of this type, thresholds of memory cells are about 0.5 volts-2.5 volts in an initial state. FIG. 20 shows the threshold states.
According to this technique, programming is executed by using the channel hot electron as follows. Initially, an H(high)-level is supplied to a data line DL shown in FIG. 26. Then, an L(low)-level is latched into a write data latch circuit DLC. The potential of a word line WL associated with the memory cells M0 through M5 rises to a Vpp (for example, 10 volts), and the potential of a bit line selection signal bitsel0 has also the potential Vpp. At this time, a bit line BL0 is in a floating state. As a result, the threshold of the memory cell M0 is kept at the low level (2.5 volts or less).
In the following operation, an L-level is supplied to the data line DL, and an H-level is latched into the write data latch circuit DLC. On the other hand, the potential of the word line WL for the memory cells M0 through M5 rises to Vpp (for example, 10 volts) . In addition, the potential of the bit line selection signal bitsell becomes Vpp and a voltage hhprg (for example, 6 volts) is supplied to a bit line BL1. Channel hot electrons are thus generated in the memory cell M1 and its threshold rises to a voltage of 5 volts or more.
On the other hand, to have a second defective address latch circuit ALC1 latch a "0", the memory cell M2 is placed in a programmed state (the threshold being 5 volts or more), and the memory cell M3 is kept in the erased state (in which the threshold is low). Also, to have a third defective address latch circuit ALC1 latch data "1", the memory cell M4 is placed in the erased state, while the memory cell M5 is kept in the programmed state.
The defective address latch circuits ALC0, ALC1, and ALC2 each latch one data by using two memory cells having different threshold states. More specifically, one data is latched using one memory cell whose threshold is 2.5 volts or less in combination with the other memory cell whose threshold is 5 volts or more.
The address latch operation will be described below with reference to FIGS. 23A, 23B, 24A, and 24B.
First, latch of data "0" by the defective address latch circuit is described below with reference to FIGS. 23A and 24A. In this case, the threshold, Vth, of the memory cell M0 is high (Vth.gtoreq.5 volts), whereas the threshold, Vth, of the memory cell M1 is low (Vth.ltoreq.2.5 volts). As indicated by a power supply turn-on waveform of FIG. 24A, when the supply voltage Vcc increases and the potential of the word line WL becomes 2.5 volts or more, an electric charge is extracted from the node A because the threshold of the memory cell M1 is low. Thus, the potential of the node A becomes 0 volts. At this time, because the threshold of the memory cell M0 is 5 volts or more, the potential of the node B is kept at a high level (2.5 volts) . As a result, the ground-side potential Vss (data "0") is supplied to the output radd.
Next, latch of data "1" by the defective address latch circuit is described below with reference to FIGS. 23B and 24B. In this case, the threshold, Vth, of the memory cell M0 is low (Vth.ltoreq.2.5 volts), whereas the threshold, Vth, of the memory cell M1 is high (Vth.gtoreq.5 volts). As indicated by a power supply turn-on waveform of FIG. 24B, when the supply voltage Vcc increases and the potential of the word line WL becomes 2.5 volts or more, an electric charge is extracted from the node B because the threshold of the memory cell M0 is low. Thus, the potential of the node B becomes 0 volts. On the other hand, because the threshold of the memory cell M1 is 5 volts or more, the potential of the node A is kept at a high level (2.5 volts) . As a result, the power supply voltage Vcc (data "1") is supplied to the output radd.
Thus, with this technique, it is possible to stably obtain two data owing to the difference between the threshold of the memory cell M0 and that of the memory cell M1.
However, the techniques according to the first and second related background arts have the following common problems (1) and (2).
(1) The address latch does not become definite until the supply voltage becomes 2.5 volts or more after the power is turned on. PA1 (2) The address latch circuit has an unstable operation when the supply voltage is lower than 2.5 volts and cannot operate at a low voltage. That is, the address latch circuit cannot operate at a voltage lower than 2.5 volts.
The problem (1) is described below in connection with the first related background art, with reference to FIGS. 21A, 21B, 22B, and 22B. When the supply voltage Vcc starts to rise but is less than 2.5 volts, as understood from FIG. 22A and 22B, the node A is placed in the state "H". Accordingly, whether the memory cell stores data "0" or "1", the output radd has the ground potential Vss. This is because as shown in FIG. 20, the upper limit of the threshold of the memory cell placed in the erased state (memory cell at "L" side) is 2.5 volts, in which case electric current does not flow through even the memory cell storing the data "1".
In the second related background art as well, the upper limit of the threshold of the memory cell in the erased state ("L" side) is also 2.5 volts as shown in FIG. 20. Thus, electric current does not flow through the memory cells M0, M1 shown in FIGS. 23A and 23B and the latching state is not stable. Whether the ground-side potential Vss or the supply voltage Vcc is output from the output radd depends on the layout of the circuit. Because inverters for signal-output are connected with the node A, the ground-side potential Vss is output from the output radd.
As described above, in both of the first and second related background arts, when the supply voltage is lower than 2.5 volts, the defective address latch circuit is incapable of correctly latching an address. Before the supply voltage rises completely up to 2.5 volts or more, the defective address latch circuit is in a state latching not an address "101" but an address "000", the latter address being for a non-defective block. Thus, at this time, if a user makes an access to erase the non-defective block corresponding to the address "000" in the memory device, the block at the address "000" is recognized erroneously as a defective block and the corresponding redundancy block at the address "000" is erroneously erased. Further, data in the non-defective block at the address "000" proper in the memory device, which the user wished to erase, remain unerased.
As is obvious, because the threshold of the memory cell in the initial state is conventionally set to the range of 0.5 volts to 2.5 volts, the memory device can malfunction when it is operated at the supply voltage lower than 2.5 volts, and in the worst case, necessary data may be erased.
The content of the problem (2) is similar to what has been described above in connection with the problem (1). That is, the memory device cannot be operated at the supply voltage lower than 2.5 volts.
In recent years, as flash memory-applied goods, more and more portable terminals such as portable telephones have been commercially available. There is a growing demand for operating the portable terminals at a low voltage to save power consumption. Accordingly, it is a very important issue to design a device operable at a low voltage.